1. Field of the Invention
The present invention relates to a capacitor component used in a semiconductor device, and more particularly to a capacitor structure, to a mounting structure of a capacitor and a semiconductor element, and to a method for manufacturing same.
2. Related Art
In the past, many capacitors have been mounted in the area surrounding an LSI device on mounting board on which semiconductor elements are mounted, in order to prevent generating of noise.
When a clock signal changing at a high frequency is generated from an LSI device, because of the resistance R and inductance L existing in the wiring between the power supply and the LSI device, a voltage drop xcex94V, given by the following equation (1), occurs.
xcex94V=Rxc3x97xcex94i+Lxc3x97di/dtxe2x80x83xe2x80x83(1)
In above relationship, R is the resistance of the wiring and the capacitor, L is the inductance thereof, and xcex94i is the change in current during the time xcex94t.
Therefore, the larger R, L, and the load change di are, or the smaller the time change dt is, the greater will be the increase in the voltage drop xcex94V. In recent years, the clock frequency of LSI devices has reached to high speed such as hundreds of megahertz. The rise time tr of pulse waveforms in digital circuitry is now equivalent to the change time dt of the load. Because the higher the clock frequency is, the shorter is the rise time tr, the larger will be the voltage drop xcex94V.
In order to make this voltage drop smaller, it is effective to connect a capacitor parallel between the LSI power line and the ground line, this capacitor generally being referred to as a decoupling capacitor. As the LSI device clock frequency increases, because the temporarily decreased voltage when there is a load change cannot be sufficiently compensated for by the power supply, a charge is supplied from a decoupling capacitor connected close to the LSI device to provide this compensation. However, because of the influence of the capacitor""s equivalent series resistance (ESR), equivalent series inductance (ESL), and the wiring resistance Rl and wiring inductance L1 in the wiring from the capacitor to the LSI device, the voltage drop xcex94V of Equation (1) occurs.
Additionally, because of the existence of ESR, ESL, R1, and L1 in the circuit, at some frequency an LC resonance occurs, the result being that the capacitor fails to function as a capacitor at higher frequencies than that above-mentioned. Thus, in addition to an increase the LSI device clock frequency, it is necessary to increase the LC resonant frequency f of the decoupling capacitor. The LC resonant frequency f is given by the following Equation (2).
f2=1/(4xcfx802xc3x97Lxc3x97C)xe2x80x83xe2x80x83(2)
For this reason, it is necessary to select as a decoupling capacitor a capacitor having a small value of C and a small value of L. A commonly used decoupling capacitor is a multilayer ceramic capacitor having a capacitance of 0.1 xcexcF or smaller, having relatively good high-frequency characteristics. A multilayer ceramic capacitor has ESR being smaller than that of an electrolytic capacitor, and also has the advantage having a smaller value of ESL. However, because the capacitance value C thereof is small, it is necessary to connect a large number of capacitors in parallel in order to achieve the required charge. However, since by merely connecting capacitors in parallel, the resonance frequency f cannot be changed, it was not possible to achieve sufficient characteristics as a decoupling capacitor because of R1 and L1 in the wiring from the capacitors to the LSI device.
Taking the example of a multiplayer ceramic capacitor commonly used as a decoupling capacitor in the past to compensate for the LSI device voltage drop, even if the values of resistance R and inductance L of the wiring is ignored, the value of capacitance C is 0.01 xcexcF and the value of ESL is 0.4 nH. Therefore, from Equation (2), it was not possible to achieve a resonant frequency f for this capacitor higher than approximately 80 MHz.
As described in the Apr. 19, 1999 issue of Nikkei Electronics (pp 144-156), it is known that as the thickness of the dielectric is reduced, the ESL is also reduced. From this fact, there have been several reports of inventions related to semiconductor devices using a thin-film capacitor (For example, Japanese Unexamined patent publication (KOKAI) No. 11-45822 and Japanese Unexamined patent publication (KOKAI) No. H8-97360. However, these did not solve the problem of the voltage drop xcex94V occurring because of the wiring resistance R1 and inductance L1 between the capacitor and the LSI device.
On the other hand, a mounting board with thin-film capacitors formed in the surface for mounting semiconductor elements so as to reduce the above-noted R1 and L1 of a wire is reported in the Japanese Unexamined patent publication (KOKAI) No. H2-203595 and Japanese Unexamined patent publication (KOKAI) No. H4-211191.
In these, however, there is the problem that there is a restriction to ceramic boards, which can withstand high temperatures encountered in fabricating the thin-film capacitors. Another problem is that a low manufacturing yield thereof was low. In Japanese Unexamined patent publication (KOKAI) No. H9-223719, there is a report of a semiconductor device in which a thin-film capacitor is formed on a surface other than a surface on which semiconductor elements are mounted. This, however, does not sufficiently reduce the values of R1 and L1 of the wiring.
As is clear from the above, in the past there was the problem of not being able to achieve sufficient frequency characteristics in capacitor components. Additionally, even in a thin-film capacitor with superior high-frequency characteristics, because of the wiring R1 and L1 between the capacitor and the LSI device, overall effective characteristics at high frequencies were insufficient. With a mounting board on which a thin-film capacitor is formed on a surface on which semiconductor elements are mounted, there is the problem of poor manufacturing yield, and the additional problems of restriction to the use of a ceramic board, and of insufficient frequency characteristics.
Accordingly, in order to solve the above-described problems, it is an object of the present invention to provide a capacitor component connected to a semiconductor element without intervening wiring, or a capacitor component connected between a flip-chip connected semiconductor element and a board. It is a further object of the present invention to provide a method for manufacturing the above-noted capacitor components. It is yet another object of the present invention to provide a semiconductor element to which a capacitor is connected, a package with a built-in capacitor or a chip-size package (CSP) with a built-in capacitor, and further to provide a method for manufacturing same. It is yet another object of the present invention to provide a structure wherein a capacitor is mounted in a space between a flip-chip connected semiconductor element and a board.
To achieve the above-noted objects, the present invention adopts the following described technical constitution.
Specifically, a capacitor according to the present invention is a capacitor used associated with a semiconductor element, this capacitor being formed by the successive laminations of a lower electrode, a dielectric thin film, an upper electrode, and an insulation cover onto an insulating substrate in this order, a plurality of through holes each being formed through the insulation substrate, the lower electrode, the dielectric thin film, the upper electrode, and the insulation cover, at positions corresponding to the input and output pads of the semiconductor element, and within a part of the plurality of through holes, either the lower electrode or the upper electrode is exposed for the purpose of connecting the input and output pads of the semiconductor element.
The above-noted insulation substrate can be made of an organic film, and can also be made of ceramic.
It is desirable that either one of the lower electrode and the upper electrode serves as a power supply plane, the other of the lower electrode and the upper electrode serving as the ground plane, and that the power supply plane and the ground plane are exposed within the through holes located at the positions each corresponding to the positions of the power and ground pads, respectively, of the semiconductor element, and that neither the lower electrode nor the upper electrode are exposed within through holes located at positions corresponding to the signal pads of the semiconductor element. It is possible to provide a dummy electrode within these through holes, which is electrically connected to neither the lower electrode nor the upper electrode. Alternatively, it is possible to provide a dummy electrode connected via a resistor to at least one of the lower electrode and the upper electrode.
It is possible to apply an adhesive to at least one of the front or rear surface of a capacitor according to the present invention.
It is possible to form a plurality of through holes at positions corresponding to positions of input and -output terminals of a semiconductor package instead of the input and output pads of the semiconductor element. In this case, the input and output terminals of the semiconductor package corresponding to the through holes can be a BGA (ball grid array) pads of a CSP (chip-size package).
It is further possible to form within the through holes a joining material for the purpose of joining the material with the input and output pads of the semiconductor element.
A semiconductor device according to the present invention has a capacitor according to the present invention connected by the above-noted joining material via either the lower electrode or the upper electrode within the through hole.
It is also possible to fill the space between the semiconductor element and the capacitor using an undersell resin, and further possible to seal the semiconductor element using a molded resin.
It is possible make the package a CSP. It is further possible to have the capacitor according to the present invention connected by the joining material via either the lower electrode or the upper electrode within the through hole to input and output terminals of the semiconductor package.
A capacitor mounting structure according to the present invention has a capacitor according to the present invention interposed between a semiconductor element and a mounting substrate, and connected by a joining material via either a lower electrode or an upper electrode within the through hole to both the semiconductor element and the mounting substrate.
In the above case, it is desirable that the spaces formed among the semiconductor element, the capacitor, and the mounting substrate be filled with underfill resin.
It is also possible for a capacitor according to the present invention to be interposed between a package and a mounting substrate, and to be connected by a joining material via either a lower electrode or an upper electrode to both the package and the mounting substrate.
It is possible to use solder, a metallic bump, an electrically conductive adhesive, or an electrically anisotropic conductive resin as the above-noted joining material.
Additionally, it is possible a capacitor according to the present invention to be interposed between a semiconductor element and a mounting substrate, and be connected to both the semiconductor element and the mounting substrate by a joining material via either a lower electrode or an upper electrode within the through hole, with an adhesive applied to the front and the rear surfaces of the capacitor serving also as an underfill resin or a sealing resin.
A method for manufacturing a capacitor according to the present invention has a step of forming an organic film on a wafer, a step of forming a film for the lower electrode, a step of patterning that film, a step of forming a dielectric thin film, a step of patterning that film, a step of forming a film for the upper electrode, a step of patterning that film, and wherein a step of peeling the organic film from the wafer carried out after when the above-noted steps had been done.
Additionally, it is possible to add a step of applying the adhesive.
Another method for manufacturing a capacitor of the present invention comprises a step of forming a lower electrode film, a step of patterning that film, a step of forming a dielectric thin film, a step of patterning that film, a step of forming an upper electrode film, a step of patterning that film, and wherein the capacitor of the present invention is produced with a roll-to-roll method.
Additionally, it is possible to add a step of applying the adhesive.
A method for manufacturing a semiconductor device according to the present invention has a step of forming an organic film on a wafer, a step of forming a lower electrode film, a step of patterning that film, a step of forming a dielectric thin film, a step of patterning that film, forming an upper electrode film, a step of patterning that film, a step of connecting a semiconductor element to the capacitor, and wherein a step of peeling the organic film from the wafer carried out after when the above-noted steps had been done.
It is possible to have an additional step of underfilling or molding, in this method.
Another method for manufacturing a semiconductor device according to the present invention is a roll-to-roll organic film manufacturing method, which includes a step of forming a lower electrode film, a step of patterning that film, a step of forming a dielectric thin film, a step of patterning that film, a step of forming an upper electrode film, a step of patterning that film, and a step of connecting a semiconductor element to the capacitor. It is possible to have an additional step of underfilling or molding.
It is further possible to include steps of distributing a joining material to the through hole, and connecting the semiconductor element.